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9502c?at42?09/2014 features ? number of keys: ? up to 16 keys, and one slider (constructed from 2 to 8 keys) ? technology: ? patented spread-spectrum charge-transfer (transverse mode) ? number of i/o lines: ? 11 (3 dedicated ? configurable for input or output, 8 shared ? output only) ? pwm control for led driving ? key outline sizes: ? 6 mm 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible ? key spacings: ? 8 mm or wider, center to center (panel thickness dependent) ? slider design: ? 2 to 8 keys placed in sequence, same design as keys ? electrode design: ? two-part electrode shapes (drive-receive); wide variety of possible layouts ? pcb layers required: ? one layer (with jumpers), two layers (no jumpers) ? electrode materials: ? pcb, fpcb, silver or carbon on film, ito on film ? panel materials: ? plastic, glass, composites, painted su rfaces (low particle density metallic paints possible) ? adjacent metal: ? compatible with grounded metal immediately next to keys ? panel thickness: ? up to 3 mm glass, 2.5 mm plastic (key size dependent) ? key sensitivity: ? individually settable via simple commands over i 2 c-compatible interface ? interface: ? i 2 c-compatible slave mode (100 khz) ? moisture tolerance: ? increased moisture tolerance based on hardware design and firmware tuning ? signal processing: ? self-calibration, auto drift compensation, noise filtering ? adjacent key suppression ? (aks ? ) technology ? applications: ? laptop, mobile, consumer appliances, pc peripheral ? this datasheet is applicable to revision 4r0 chips only ? operating voltage: ? 1.8 v ? 5.5 v ? package: ? 28-pin 4 4 mm qfn rohs compliant atmel at42qt2160 16-key qmatrix touch sensor ic datasheet
2 at42qt2160 [datasheet] 9502c?at42?09/2014 1. pinout and schematic 1.1 pinout configuration 1.2 pinout descriptions gpio1 y1a y0a rst vref x0 x2 gpio2 gpio3 vss vdd x6 vss y0b y1b 1 2 3 4 5 6 7 15 16 17 18 19 20 21 28 27 26 25 24 23 22 8 9 14 13 12 11 10 qt2160 x7 change x3 x4 vdd i2ca0 smp x1 x5 vdd i2ca1 sda scl table 1-1. pin listing pin name type comments if unused, connect to? 1 gpio2 i/o general purpose input/output 2 ? 2 gpio3 i/o general purpose input/output 3 ? 3 vdd p power ? 4 vss p supply ground ? 5 x6 o x matrix drive line / shared gpo x6 leave open 6 x7 o x matrix drive line / shared gpo x7 leave open 7 change od state change notification leave open 8 vref p supply ground ? 9 smp o sample output. ? 10 x0 o x matrix drive line / shared gpo x0 leave open 11 x1 o x matrix drive line / shared gpo x1 leave open
3 at42qt2160 [datasheet] 9502c?at42?09/2014 i input only o output only, push-pull i/o input/output od open drain output p ground or power 12 x2 o x matrix drive line / shared gpo x2 leave open 13 x3 o x matrix drive line / shared gpo x3 leave open 14 x4 o x matrix drive line / shared gpo x4 leave open 15 x5 o x matrix drive line / shared gpo x5 leave open 16 vdd p power ? 17 vdd p power ? 18 vss p supply ground ? 19 y0b i/o y line connection leave open 20 y1b i/o y line connection leave open 21 i2ca0 i i 2 c address select ? 22 i2ca1 i i 2 c address select ? 23 sda od serial interface data ? 24 scl od serial interface clock ? 25 rst i reset low; has internal 30k - 60k pull-up leave open or vdd 26 y0a i/o y line connection leave open 27 y1a i/o y line connection leave open 28 gpio1 i/o general purpose input/output 1 ? table 1-1. pin listing (continued) pin name type comments if unused, connect to?
4 at42qt2160 [datasheet] 9502c?at42?09/2014 1.3 schematic figure 1-1. typical circuit check the following sections for component values: ? section 3.3 on page 8 : cs capacitors (cs0 ? cs1) ? section 3.5 on page 10 : sample resistors (rs0 ? rs1) ? section 3.7 on page 10 : matrix resistors (rx0 ? rx7, ry0 ? ry1) ? section 3.11 on page 15 : voltage levels ? section 5.4 on page 22 : sda, scl pull-up resistors (rp) ? section 5.5 on page 22 : change resistor (rchg) ? section 5.2 on page 21 : i 2 c addresses rp rp matrix y scan in matrix x drive rchg vreg rx0 rx3 rx6 vdd scl sda rs1 cs0 cs1 ry1 rx2 rx1 rx7 rx5 vunreg vdd vdd ry0 rx4 change i2c i2c address select qt2160 rs0 general purpose inputs/outputs notes: 1) the central pad on the underside of the chip is a vss pin and should be connected to ground. do not put any other tracks underneath the body of the chip. 2) it is important to place all rx, ry, cs and rs components physically near to the chip. 3) leave yna, ynb unconnected if not used. follow regulator manufacturers recommended values for input and output bypass capacitors. tightly wire a 100nf bypass capacitor between vdd and vss (pins 3 and 4).
5 at42qt2160 [datasheet] 9502c?at42?09/2014 figure 1-2. inputs/outputs * low-pass filter can be added to filter out burst pulses on shared gpos (x0 x7) gpio / x where = 1 3 = 0 7 nm n m gpio / x where = 1 3 = 0 7 nm n m gpio where = 1 3 n n gpio where = 1 3 n n
6 at42qt2160 [datasheet] 9502c?at42?09/2014 2. overview 2.1 introduction the at42qt2160-mmu (qt2160) is designed for use with up to 16 keys and a slider (constructed from 2 keys up to 8 keys). there are three dedicated general purpose i nput/outputs (gpios) which can be used as inputs for mechanical switches or as driven outputs. there are eight shared general purpose outputs (gpos) (x0 ? x7) which are driven outputs only. there is pwm control for each gpio/gpos. the qt2160 device is a digital burst mode charge-transfer (qt?) sensor designed specifically for matrix layout touch controls; it includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions. only a few external parts are required for operation. the entire circuit can be built within a few square centimeters of single-sided pcb area. cem-1 and fr 1 punched, single-sided materials can be used for the lowest possible cost. the pcb rear can be mounted flush on the back of a glass or plastic panel using a conventional adhesive, such as 3m vhb two-sided adhesive acrylic film. the qt2160 technology employs transverse charge-transfe r sensing electrode designs which can be made very compact and are easily wired. charge is forced from an em itting electrode into the overlying panel dielectric, and then collected on a receiver electrode (see figure 2-1 ). this directs the charge into a sampling capacitor which is then converted directly to digital form, without the use of amplifiers. the keys are configured in a matrix format that minimi zes the number of required scan lines and device pins. the key electrodes can be designed into a conventional print ed circuit board (pcb) or flex ible printed circuit board (fpcb) as a copper pattern, or as printed conductive ink on plastic film. the device uses an i 2 c-compatible interface to allow key data to be extracted and to permit individual key parameter setup. the command structure is designed to minimize the amount of data traffic while maximizing the amount of information conveyed. in addition to normal operating and setup functions the device can also report back actual signal strengths. figure 2-1. field flow between x and y elements 2.2 keys and slider the qt2160 is capable of a maximum of 16 keys. these can be located anywhere within an electrical grid of eight x and two y scan lines. a lesser number of enabled keys will cause any unused acquisition burst time slots to be pared from the sampling sequence, to optimize acquire speed and lessen power consumption. thus, if only eight keys are actually enabled, only eight timeslots are used for scanning. additional processing can be done on the keys to form a slider. the slider must start at x0 and use only y0. the slider can consist of a minimum of two keys and a maximum of eight keys. 2.3 enabling/disabling keys keys can be enabled by setting a non-zero burst length. a zero burst length disables the key. overlying panel cmos driver x element y element
7 at42qt2160 [datasheet] 9502c?at42?09/2014 2.4 moisture tolerance the presence of water (condensation, sweat, spilt water, and so on) on a sensor can alter the signal values measured and thereby affect the performance of any capacitive device. the moisture tolerance of qtouch devices can be improved by designing the hardware and fine-tuning the firmware following the recommendations in the application note atmel avr3002: moisture tolerant qtouch design ( www.atmel.com/images/doc42017.pdf ).
8 at42qt2160 [datasheet] 9502c?at42?09/2014 3. hardware and functional 3.1 matrix scan sequence the circuit operates by scanning each key sequentially, key by key. key scanning begins with location x = 0, y = 0 (key 0). x axis keys are known as rows while y axis keys are referred to as columns although this has no reflection on actual wiring. keys are scanned sequentially by row, for example the sequence x0y0 x1y0 ? x7y0, x0y1, x1y1... and so on. keys are also numbered from 0 ? 15. key 0 is located at x0y0. table 3-1 shows the key numbering. each key is sampled in a burst of acquisition pulses whose length is determined by the setups parameter bl ( table 7-1 on page 36 ); this can be set on a per-key basis. a burst is completed entirely before the next key is sampled; at the end of each burst the resulting signal is converted to digital form and processed. the burst length directly impacts key gain; each key can have a unique burst length in order to allow tailoring of key sensitivity on a key-by-key basis. 3.2 burst paring keys that are disabled by setting their burst length to zero have their bursts removed from the scan sequence to save scan time and thus power. the qt2160 operates on a fixed 16 ms cycle and will go to sleep after all acquisitions and processing is done till the next 16ms cycle starts. as a consequence, the fewer keys, the less power is consumed. 3.3 cs sample capacitor operation cs capacitors (cs0 ? cs1) absorb charge from the key electrodes on the rising edge of each x pulse. on each falling edge of x, the y matrix line is clamped to ground to allow the electrode and wiring charges to neutralize in preparation for the next pulse. with each x pulse charge accumulates on cs causing a staircase increase in its differential voltage. after the burst completes, the device clamps the y line to ground causing the opposite terminal to go negative. the charge on cs is then measured using an external resist or to ramp the negative te rminal upwards until a zero crossing is achieved. the time required to zero cross becomes the measurement result. the cs capacitors should be connected as shown in figure 1-1 on page 4 . the value of these capacitors is not critical but 4.7 nf is recommended for most cases. they should be 10% x7r ceramic. if the transverse capacitive coupling from x to y is large enough the voltage on a cs capacitor can saturate, destroying gain. in such cases the burst length should be reduced and/or the cs value increased. see section 3.4 . if a y line is not used its corresponding cs capacitor may be omitted and the pins left floating. 3.4 sample capacitor saturation cs voltage saturation at a pin ynb is shown in figure 3.5 . saturation begins to occur when the voltage at a ynb pin becomes more negative than ?0.25 v at the end of the burst. this nonlinearity is caused by excessive voltage accumulation on cs inducing conduction in the pin protecti on diodes. this badly saturated signal destroys key gain and introduces a strong thermal coefficient which can cause phantom detection. the cause of this is either from the burst length being too long, the cs value being too small, or the x-y transfer coupling being too large. solutions include loosening up the key structure interleaving, more separation of the x and y lines on the pcb, increasing cs, and decreasing the burst length. table 3-1. key numbers x7 x6 x5 x4 x3 x2 x1 x0 y0 7 6 5 4 3 2 1 0 key numbers y1 15 14 13 12 11 10 9 8
9 at42qt2160 [datasheet] 9502c?at42?09/2014 figure 3-1. vcs ? nonlinear during burst increasing cs will make the part slower; decreasing burst length will make it less sensitive. a better pcb layout and a looser key structure (up to a point) have no negative effects. cs voltages should be observed on an oscilloscope with the matrix layer bonded to the panel material; if the rs side of any cs ramps more negative than ?0.25 v during any burst (not counting overshoot spikes which are probe artifacts), there is a potential saturation problem. figure 3-2. vcs ? poor gain, nonlinear during burst figure 3.5 shows a defective waveform similar to that of figure 3.5 , but in this case the distortion is caused by excessive stray capacitance coupling from the y line to ac ground; for example, from running too near and too far alongside a ground trace, ground plane, or other traces. the excess coupling causes the charge-transfer effect to dissipate a significant portion of the received charge from a key into the stray capacitance. this phenomenon is more subtle; it can be best detected by increasing bl to a high count and watching what the waveform does as it descends towards and below ?0.25 v. the waveform will appear deceptively straight, but it will slowly start to flatten even before the ?0.25 v level is reached. figure 3-3. vcs ? correct x drive ynb x drive ynb x drive ynb
10 at42qt2160 [datasheet] 9502c?at42?09/2014 a correct waveform is shown in figure 3.5 on page 10 . note that the bottom edge of the bottom trace is substantially straight (ignoring the downward spikes). unlike other qt circuits, the cs capacitor values on qt2160 devices have no effect on conversion gain. however, they do affect conversion time. unused y lines should be left open. 3.5 sample resistors the sample resistors (rs0 ? rs1) are used to perform single-slope adc conversion of the acquired charge on each cs capacitor. these resistors directly control acquisition gain; larger values of rs will proportionately increase signal gain. for most applications rs should be 1 m ? . unused y lines do not require an rs resistor. 3.6 signal levels the signal values should normally be in the range of 200 to 750 counts with properly designed key shapes and values of rs. however, long adjacent runs of x and y lines can also artificially boost the signal values, and induce signal saturation; this is to be avoided. the x-to-y co upling should come mostly from intra-key electrode coupling, not from stray x-to-y trace coupling. the signal swing from the smallest finger touch should preferably exceed 8 counts, with 12 being a reasonable target. the signal threshold setting (nthr) should be se t to a value guaranteed to be less than the signal swing caused by the smallest touch. increasing the burst length (bl) parameter will increase t he signal strengths, as will increasing the sampling resistor (rs) values. 3.7 matrix series resistors the x and y matrix scan lines can use series resistors (rx0 ? rx7 and ry0 ? ry1 respectively) for improved emc performance ( figure 1-1 on page 4 ). x drive lines require rx in most cases to reduce edge ra tes and thus reduce rf emissions. values range from 1 k ? to 20 k ? , typically 1 k ? . y lines need ry to reduce emc susceptibility problems and in some extreme cases, esd. typical y values are about 1k ? . y resistors act to reduce noise susceptibility problem s by forming a natural low-pass filter with the cs capacitors. it is essential that the rx and ry resistors and cs capacitors be placed very close to the chip. placing these parts more than a few millimeters away opens the circuit up to high frequency interference problems (above 20 mhz) as the trace lengths between the components and the chip start to act as rf antennae. the upper limits of rx and ry are reached when the signal level and hence key sensitivity are clearly reduced. the limits of rx and ry will depend on key geometry and stray ca pacitance, and thus an oscilloscope is required to determine optimum values of both.
11 at42qt2160 [datasheet] 9502c?at42?09/2014 figure 3-4. drive pulse roll-off and dwell time dwell time is the duration in which charge coupled from x to y is captured ( figure 3-4 on page 11 ). increasing rx values will cause the leading edge of the x pulses to increa singly roll off, causing the loss of captured charge (and hence loss of signal strength) from the keys. the dwell time is a minimum of 250 ns. if the x pulses have not settled within 250 ns, key gain will be reduced; if this happens, either the stray capacitance on the x line(s) should be reduced (by a layout change, for example by reducing x line exposure to nearby ground planes or traces), or, the rx resistor needs to be reduced in value (or a combination of both approaches). one way to determine x line settling time is to monitor the fi elds using a patch of metal foil or a small coin over the key ( figure 3-5 on page 11 ). only one key along a particular x line needs to be observed, 250 ns dwell time should exceed the observed 95% settling of the x-pulse by 25% or more. in almost all cases, ry should be set equal to rx, which will ensure that the charge on the y line is fully captured into the cs capacitor. figure 3-5. probing x-drive waveforms with a coin x drive y gate dwell time lost charge due to inadequate settling before end of dwell time
12 at42qt2160 [datasheet] 9502c?at42?09/2014 3.8 key design circuits can be constructed out of a variety of materials including conventional fr-4, flexible printed circuit boards (fpcb), silver silk-screened on pet plastic film, and even inexpensive punched single-sided cem-1 and fr-2. the actual internal pattern style is not as important as the need to achieve regular x and y widths and spacings of sufficient size to cover the desired graphical key area or a little bit more; ~3mm oversize is acceptable in most cases, since the key?s electric fields drop off near the edges any way. the overall key size can range from 6 mm x 6 mm up to 100 mm x 100 mm but these are not hard limits. the keys can be any shape including round, rectangular, square, etc. the internal pattern can be interdigitated as shown in figure 3-6 . for small, dense keypads, electrodes such as shown in the lower half of figure 3-6 can be used. where the panels are thin (under 2 mm thick) the electrode density can be quite high. for better surface moisture suppression, the outer perimeter of x should be as wide as possible, and there should be no ground planes near the keys. the variable t in this drawing represents the total thickness of all materials that the keys must penetrate.
13 at42qt2160 [datasheet] 9502c?at42?09/2014 figure 3-6. recommended key structure note: t should ideally be similar to the complete thickness the fields need to penetrate to the touch surface. smaller dimensions will also work but will give less signal strength. if in doubt, make the pattern coarser. the lower figure shows a simpler structure used for compact key layouts, for example for mobile phones. a layout with a common x drive and two receive electrodes is depicted ?t ?t ?t t x x0 y y0 y1 y2
14 at42qt2160 [datasheet] 9502c?at42?09/2014 3.9 setting the slider 3.9.1 introduction groups of keys can be configured as a slider, in addition to their use as keys. the slider uses the y0 line of the matrix and must start at x0, with the keys placed in consecutive numerical order. the slider can take up a programmable number of keys on the y0 line. the remaining keys on that y line behave as normal. positional data is calculated in a customizable range of 2 bi ts (0 ? 3) to 8 bits (0 ? 255). geometric constraints may mean that the data will not reach the full range. thinner dielectric or the use of more keys in a slider will increase the data range towards the ends. stability of the reported position will be dependent on the amount of signal on the slider keys. running at higher resolutions, with a thick panel might produce a fluctuating reported position. key sizes should be in the 5 ? 7mm range when used in the slider to get the best linearity. the slider should be made up of however many of these elements are required to fit their dimensions. the slider will be treated as an object in the adjacent ke y suppression (aks) groupings. the keys in the slider would normally be set to the same burst length and threshold, although adjustments can be made in these at the expense of linearity. 3.9.2 aks technology and the slider there can be up to three aks groups, implemented so that only one key in each group may be reported as being touched at an y one time. the aks tech nique will lock onto the domi nant key, and unt il this key is released, other keys in the group will not be reported as in detection. this allows a user to slide a finger across multiple keys with only the dominant key reporting touch. each key may be in one of the groups 1 ? 3, or in group 0 meaning that it is not aks enabled. keys in the slider are not able to use aks technique against each other. this is necessary to enable smooth scrolling. multiple keys within the slider can be in detect at the same time, regardless of the aks settings. the aks technique will, however, work against keys outside the object or within another object. for example, if a slider is in the same aks group as keys, then touching anywhere on the slider will cause the aks technique to suppress the keys. similarly touching the keys first will suppress the slider. note: for normal operation all keys in the slider should be placed in the same aks group. 3.10 pcb layout, construction 3.10.1 overview it is best to place the chip near the touch keys on the same pcb so as to reduce x and y trace lengths, thereby reducing the chances for emc problems. long connection traces act as rf antennae. the y (receive) lines are much more susceptible to noise pickup than the x (drive) lines. even more importantly, all signal related discrete parts (resistors and capacitors) should be very close to the body of the chip. wiring between the chip and the various resistor s and capacitors should be as short and direct as possible to suppress noise pickup. ground planes, if used, should be placed under or around t he qt chip itself and the associated resistors and capacitors in the circuit, under or around the power supply, and back to a connector. ground planes can be used to shield against radiated noise, but at the expense of a reduction in sensitivity as described previously. note: when using ground planes/floods, parasitic capacitance on y lines can lead to reduced charge-transfer efficiency. for noise suppression, ground planes/floods can be beneficial around and between keys on the touch side of the pcb. however, it is advisable to route y lines on the pcb layer furthest away from the plane/flood, to reduce parasitic capacitance. cross-hatched ground patterns can act as effective shields, while helping to reduce parasitic capacitance. ground planes/floods around the chip are generally acceptable, taking into account the same considerations as for the y line parasitics.
15 at42qt2160 [datasheet] 9502c?at42?09/2014 3.10.2 led traces and other switching signals digital switching signals near the y lines will induce trans ients into the acquired signals, deteriorating the snr performance of the device. such signals should be routed away from the y lines, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). led terminals which are multiplexed or switched into a float ing state and which are within or physically very near a key structure (even if on another nearby pcb) should be bypassed to either vss or vdd with at least a 10 nf capacitor to suppress capacitive coupling effects which can induce false signal shifts. the bypass capacitor does not need to be next to the led, in fact it can be quite distant. the bypass capacitor is noncritical and can be of any type. led terminals which are constantly connected to vss or vdd do not need further bypassing. 3.10.3 tracks the central pad on the underside of the chip should be connected to ground. do not run any tracks underneath the body of the chip, only ground. figure 3-7. position of tracks 3.10.4 pcb cleanliness all capacitive sensors should be treated as highly sensitive circuits which can be influenced by stray conductive leakage paths. qt devices have a basic resolution in the femtofarad range; in this region, there is no such thing as ?clean flux". flux absorbs moisture and becomes conductive between solder joints, causing signal drift and resultant false detections or transient losses of sensitivity or in stability. conformal coatings will trap in existing amounts of moisture which will then become highly temperature sensitive. the designer should specify ultrasonic cleaning as part of the manufacturing process, and in cases where a high level of humidity is anticipated, the use of conformal coatings after cleaning to keep out moisture. 3.11 power supply considerations see section 9.2 on page 43 for the vdd range and short-term power supply fluctuations. if the power supply fluctuates slowly with temperature, the device will track and compensate for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift co mpensation mechanism will not be able to keep up, causing sensitivity anomalies or false detections. as the device uses the power supply itself as an analog reference, the power should be very clean and come from a separate regulator. a standard inexpensive low dropout (ldo) type regulator should be used that is not also used to power other loads such as leds, relays, or other high current devices. load shifts on the output of the ldo can cause vdd to fluctuate enough to cause false detection or sensitivity shifts. caution: a regulator ic shared with other logic devices can result in erratic operation and is not advised. example of good tracking example of bad tracking
16 at42qt2160 [datasheet] 9502c?at42?09/2014 a regulator can be shared among two or more qt devices on one board. refer to page 4 for suggested regulator manufacturers. a single ceramic 0.1 f bypass capacitor, with short traces, should be placed very close to supply pins 3 and 4 of the ic. failure to do so can result in device oscillation, high current consumption, erratic operation, and so on. pins 16 and 17 do not require bypassing if the traces between these pins and power traces are short. suggested regulator manufacturers: ? toko (xc6215 series) ? seiko (s817 series) ? bcdsemi (ap2121 series) 3.12 startup/calibration times the device requires initialization times of approximately 70 ms. the change line will go low and calibration will start (takes 15 matrix scans), after this start up period is over. 3.13 calibration calibration does not occur periodically. keys are only calibrated on power-up and when: ? enabled and ? held in detect for too long. the negative recalibrat ion delay (nrd) period is specified by the user or ? the signal delta value is greater than the positive thre shold value, defined as reference value plus three- quarters of the negative threshold or ? the user issues a recalibrate command an interrupt on the change pin occurs when there is a change in the key status bytes. an interrupt will occur on calibration only if at least one of the keys or objects was in detect as recalibration will then cause a status change. 3.14 reset input the rst pin can be used to reset the device to simulate a power-down cycle, in order to bring the device up into a known state should communications with the device be lost. the pin is active low, and a low pulse lasting at least 10s must be applied to this pin to cause a reset. if an external hardware reset is not used, the reset pin may be connected to vdd. 3.15 spread spectrum acquisitions qt2160 uses spread-spectrum burst modulation. this has the effect of drastically reducing the possibility of emi effects on the sensor keys, while simultaneously spreading rf emissions. this feature is hard-wired into the device and cannot be disabled or modified. spread spectrum is configured as a frequency chirp over a wide range of frequencies for robust operation. 3.16 detection integrator see also section 3.2 on page 8 . the device features a detection integration mechanism, which acts to confirm a detection in a robust fashion. a per- key counter is incremented each time the key has exceeded its threshold and stayed there for a number of acquisitions. when this counter reaches a preset limit the key is finally declared to be touched.
17 at42qt2160 [datasheet] 9502c?at42?09/2014 for example, if the limit value is 10, then the device has to exceed its threshold and stay there for 10 acquisitions in succession without going below the threshold level, before the key is declared to be touched. if on any acquisition the signal is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. 3.17 sleep the device operates on a fixed 16 ms cycle time basis. the device will perform a set of measurements and then sleep for the rest of the cycle to conserve power. there are two user-configurable sleep modes; low power (lp) mode and sleep mode. the lp setting (see section 3.2 on page 8 ) is used for conserving power when there are no touches and is set to be a long time period. this will determine how often the device wakes up to do drift compensation. it also determines the maximum response time to the first touch after inactivity. when a valid touch is registered, the device enters minimum cycle time (16 ms) for a faster response to key touch and object operation. the device will stay in this mode if it continues to see keys being touched and released. there is a user-selectable inactivity timeout; the awake timeout. the measurement period needs to be shorter than the 16 ms fixed cycle time for optimum operation. if the measurement time exceeds the 16 ms fixed cycle time, a cy cle overrun bit is set in the general status register. the qt2160 will still operate if the 16 ms fixed cycle time is exceeded, but the timing for the timed parameters, for example, drift compensation negative recalibration time out, and so on, will slightly change. a low power setting of zero causes the device to enter an ultra-low power mode ( sleep ), where no measurements are carried out. sleep mode also stops the internal watchdog timer, so that the part is totally dormant, and current drain is <2 a. the pwm function will not be carried out during sleep, therefore it is recommended driving the gpios/gpos to known states before entering sleep mode. the qt2160 wakes from sleep mode if there is an address match on the i 2 c bus, a hardware reset on the rst pin or an lp mode is set. if the wake option is set for the dedicated gpio inputs, then the qt2160 will trigger the change line if a change in status (either positive or negative going edge) of the respective gpio is detected, in sleep mode. 3.18 general purpos e inputs/outputs there are three dedicated gpios (gpio1 ? 3) and eight gpos shared with x lines (x0 ? 7). shared gpos are always outputs, whereas dedicated gpios can be set to be outputs or inputs. gpios set to input can be used for reading dome switches or logic signals. outputs can be used to drive leds, or other devices. it is recommended driving external devices th rough the use of bipolar transistors or mosfets, so as not to affect capacitive sensing if a load fluctuates the power rail by drawing/sinking too much current. all gpos and gpios set to output can be pwm driven, if the corresponding pwm bit is set. note that the pwm duty cycle will be an approximation, as gpios will not be switched during acquisition bursts. the dedicated gpios have a wake option, that if enabled will enable dedicated gpios set as inputs, to be read in sleep mode. note that shared gpos (x0 ? x7) are driven by the burst pulses during acquisition bursts, if the corresponding x line is used in the keys/slider. a low pass filter can be inserted to eliminate these burst pulses, as shown in figure 1-2 on page 5 .
18 at42qt2160 [datasheet] 9502c?at42?09/2014 4. i 2 c operation the device communicates with the host over an i 2 c bus. the following sections give an overview of the bus; more detailed information is available from www.i2c-bus.org. devices are connected to the i 2 c bus as shown in figure 4- 1 . both bus lines are connected to vdd via pull-up resistors. the bus drivers of all i 2 c devices must be open-drain type. this implements a wired and function that allows any and all devices to drive the bus, one at a time. a low level on the bus is generated when a device outputs a zero. figure 4-1. i 2 c interface bus 4.1 transferring data bits each data bit transferred on the bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high; the only exception to this rule is for generating start and stop conditions. figure 4-2. data transfer device 1 device 2 device 3 device n r1 r2 vdd sda scl sda scl data stable data stable data change
19 at42qt2160 [datasheet] 9502c?at42?09/2014 4.2 start and stop conditions the host initiates and terminates a data transmission. the transmission is initiated when the host issues a start condition on the bus, and is terminated when the host issues a stop condition. between the start and stop conditions, the bus is considered busy. as shown in figure 4-3 , start and stop conditions are signaled by changing the level of the sda line when the scl line is high. figure 4-3. start and stop conditions 4.3 address byte format all address bytes are 9 bits long, consisting of 7 addre ss bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read operation is perfo rmed, otherwise a write operation is performed. when the device recognizes that it is being addressed, it will acknowledge by pulling sda low in the ninth scl (ack) cycle. an address byte consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the most significant bit of the address byte is transmitted first. the address sent by the host must be consistent with that selected with the option jumpers. figure 4-4. address byte format sda scl start stop addr msb addr lsb r/w ack sda scl start 12 789
20 at42qt2160 [datasheet] 9502c?at42?09/2014 4.4 data byte format all data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. during a data transfer, the host generates the clock and the start and stop conditions, while the receiver is responsible for acknowledging the reception. an acknowledge (ack) is signaled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signaled. figure 4-5. data byte format 4.5 combining address and data bytes into a transmission a transmission consists of a start co ndition, an sla+r/w, one or more data bytes and a stop condition. the wired anding of the scl line is used to implement handshaking between the host and the device. the device extends the scl low period by pulling the scl line low when ever it needs extra time for processing between the data transmissions. note: each write or read cycle must end with a stop condition. the device may not respond correctly if a cycle is terminated by a new start condition. figure 4-6 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop. figure 4-6. byte transmission data msb data lsb ack aggregate sda scl from master 12 789 sda from transmitter sda from receiver data byte stop or data byte next sla+r/w data msb data lsb ack 12 789 addr msb addr lsb r/w ack sda scl start 12 789 sla+rw data byte sto
21 at42qt2160 [datasheet] 9502c?at42?09/2014 5. interfaces 5.1 i 2 c protocol the i 2 c protocol is based around access to an address table and supports multi-byte reads and writes. note: each write or read cycle must end with a stop condition. the qt2160 may not respond correctly if a cycle is terminated by a new start condition. 5.2 i 2 c addresses four preset i 2 c addresses are selectable through pin i2ca0 and i2ca1 ( table 5-1 ). 5.3 data read/write 5.3.1 writing data to the device the sequence of events required to write data to the device is shown next. key: the host initiates the transfer by sending the start conditi on, and follows this by sending the slave address of the device together with the write-bit. the device sends an ack. the host then sends the memory address within the device it wishes to write to. the device sends an ack. the host transmits one or more data bytes; each will be acknowledged by the device. if the host sends more than one data byte, they will be written to consecutive memory addresses. the device automatically increments the target memory address after writ ing each data byte. after writing the last data byte, the host should send the stop condition. table 5-1. i 2 c addresses i2ca1 i2ca0 address 0 0 0x0d 0 1 0x17 1 0 0x44 1 1 0x6b s start condition sla+w slave address plus write bit a acknowledge bit memaddress target memory address within device data data to be written p stop condition sla+w memaddress aa s data a p host to device device tx to host
22 at42qt2160 [datasheet] 9502c?at42?09/2014 the host should not try to write beyond address 255 because the device will not increment the internal memory address beyond this. 5.3.2 reading data from the device the sequence of events required to read data from the device is shown next. the host initiates the transfer by sending the start condition, and follows this by sending the slave address of the device together with the write-bit. the device sends an ack. the host then sends the memory address within the device it wishes to read from. the device sends an ack. the host must then send a stop and a start condition followed by the slave address again but this time accompanied by the read-bit. the device will return an ack, followed by a data byte. the host must return either an ack or nack. if the host returns an ack, the device will subsequently transmit the data byte from the next address. each time a data byte is transmitted, the device automati cally increments the internal address. the device will continue to return data bytes until the host responds with a nack. the host should terminate the transfer by issuing the stop condition. 5.4 sda, scl the i 2 c bus transmits data and clock with sda and scl. they are open-drain; that is i 2 c master and slave devices can only drive these lines low or leave them open. the te rmination resistors (rp) pull the line up to vdd if no i 2 c device is pulling it down. the termination resistors commonly range from 1 k ? to 10 k ? ? and should be chosen so that the rise times on sda and scl meet the i 2 c specifications (1 s maximum). 5.5 change pin the change pin is an active low open drain output that can be used to alert the host of any changes to any of the 5 status bytes (address 2 to 6), thus reducing the need for wasteful i 2 c communications. after setting up the qt2160, the host can simply not communicate with the device, except when the change pin goes active. change goes inactive again only when the host performs a read from all status bytes which have changed. poll rate: the host can make use of the change pin output to initiate a communication; this will guarantee the optimal polling rate. if the host cannot make use of the change pin, the poll rate should be no faster than once per matrix scan (see section 9.4 on page 44 ). anything faster will not provide new information and will slow down the chip operation. the change pin requires a pull-up resistor, with a typical value of ~100 k ? . sla+w memaddress aa s s sla+r a a p host to device device tx to host p a a data 1 data 2 data n
23 at42qt2160 [datasheet] 9502c?at42?09/2014 6. communications protocol 6.1 introduction the device is address mapped. all communications consist of wr ites to, and reads from, locations in an 8-bit address map. table 6-1 shows the address map of qt2160. table 6-1. memory map address use access 0 chip id read 1 major/minor code version read 2 general status read 3 key status 1 read 4 key status 2 read 5 slider touch position read 6 gpio read read 7 sub-revision ? 8?9 reserved ? 0x00 ? 10 calibrate read/write 11 reset read/write 12 lp mode read/write 13 burst repetition read/write 14 reserved ? 0x00 read/write 15 neg drift compensation read/write 16 pos drift compensation read/write 17 normal di limit read/write 18 neg recal delay read/write 19 drift hold time/awake read/write 20 slider control read/write 21 slider options read/write 22?37 key 0 ? 15 key control read/write 38?53 key 0 ? 15 neg threshold read/write 54?69 key 0 ? 15 burst length read/write 70 gpio/gpo drive 1 read/write 71 gpio/gpo drive 2 read/write 72 reserved - 0x00 read/write 73 gpio direction 2 read/write
24 at42qt2160 [datasheet] 9502c?at42?09/2014 note: reserved areas can be read or written to, to simplify communications. if written to, only write 0x00. 6.2 address 0: chip id there is an 8-bit chip id, which is set at 0x11. 6.3 address 1: code version there is an 8-bit major and minor version of firmware code revision. the top nibble of the firmware version register contains the major version ( 4 .0) and the bottom nibble contains the minor version (4. 0 ). 6.4 address 2: general status 74 gpio/gpo pwm 1 read/write 75 gpio/gpo pwm 2 read/write 76 pwm level read/write 77 gpio wake read/write 78 common change keys 1 read/write 79 common change keys 2 read/write 80?99 reserved ? 0x00 ? 100 ? 131 key 0 ? 15 signals read 132 ? 163 key 0 ? 15 references read table 6-1. memory map (continued) address use access table 6-2. chip id address b7 b6 b5 b4 b3 b2 b1 b0 0 chip id table 6-3. code version address b7 b6 b5 b4 b3 b2 b1 b0 1 major version minor version table 6-4. general status address b7 b6 b5 b4 b3 b2 b1 b0 2 reset cycle overrun 0 0 0 0 cc sdet
25 at42qt2160 [datasheet] 9502c?at42?09/2014 these bits indicate the general status of the device. a change in this byte will cause the change line to trigger. reset: this bit is set after a reset. this bit is clear after this byte is read back by the host. cycle overrun: this bit is set if the cycle time is more than 16 ms. it will be cleared when the cycle time is less than 16ms. note: holding any of the i 2 c lines, for clock stretching or other purposes, will increase the cycle time. cc: this common change bit is set if all the selected keys (address 78 ? 79) have a signal change of more than half the detection threshold, nthr. the cc bit is not debounced. this bit can be used to indicate a common change in signals, for example, in a notebook application, where the cover is closing, so that the host can suppress key detections. note: the cc bit will be set to 1 if no keys are selected to be in the common change group (see section 6.27 on page 34 ). sdet: this bit is set if a touch is detected on the slider. 6.5 address 3 ? 4: key status address 3: detect status for keys 0 ? 7 address 4: detect status for keys 8 ? 15 each location indicates all keys in detection, if any, as a bit field; touched keys report as 1, untouched or disabled keys report as 0. a change in this byte will cause the change line to trigger. 6.6 address 5: slider touch position position: last position of the touch on the slider a change in this byte will cause the change line to trigger. 6.7 address 6: gpio read table 6-5. key status and numbering address b7 b6 b5 b4 b3 b2 b1 b0 3 k7 k6 k5 k4 k3 k2 k1 k0 4 k15 k14 k13 k12 k11 k10 k9 k8 table 6-6. slider touch position address b7 b6 b5 b4 b3 b2 b1 b0 5 position table 6-7. gpio read address b7 b6 b5 b4 b3 b2 b1 b0 6 0 0 0 gpio3 gpio2 gpio1 0 0
26 at42qt2160 [datasheet] 9502c?at42?09/2014 gpio1 ? 3: if gpio1 ? 3 are set as inputs, returns the logic level on the respective pin. if a gpio is set as an output, the respective bit in gpio read will always report 0. gpios set as inputs are only read once every cycle, that is, every 16ms. a change in this byte will cause the change line to trigger. 6.8 address 7: sub-revision this is an 8-bit sub-revision number that follows the code version (for example, 4.0. 0 ). 6.9 address 10: calibrate writing any non-zero value into this address will tri gger the qt2160 to start a recalibration on all enabled keys. 6.10 address 11: reset any non-zero value will trigger the device to reset. after a reset, the device will revert to default settings. after receiving a reset command the qt2160 will start not acknowledging i 2 c communications and make change inactive within 16ms. the chip will reset after another ~16ms. 6.11 address 12: lp mode lp mode sets the sleep time between bursts. a higher value causes more sleep time between acquisitions resulting in lower power consumption, but slower response time. table 6-8. sub-revision address b7 b6 b5 b4 b3 b2 b1 b0 7 sub-revision table 6-9. calibrate address b7 b6 b5 b4 b3 b2 b1 b0 10 calibrate table 6-10. reset address b7 b6 b5 b4 b3 b2 b1 b0 11 reset table 6-11. lp mode address b7 b6 b5 b4 b3 b2 b1 b0 12 lp_mode
27 at42qt2160 [datasheet] 9502c?at42?09/2014 the values are between 1 and 255, with each incrementing the sleep time by 16 ms steps. for example, 1 = 16 ms lp, 2 = 32 ms lp, 3 = 48 ms lp, and so on. a value of zero causes the device to enter an ultra- low power mode (sleep), where no measurements are carried out (see section 3.17 on page 17 ). the qt2160 is designed to sleep as much as possible to conserve power. note: the longer the lp mode, the longer the response time at first touch. the response time for the first touch includes the digital filter settling time (a few measurement cycles) and the di process. above 256 ms lp mode the power consumption does not reduce as much, even with longer lp mode durations. refer to table 9-1 on page 45 for typical power consumptions. default value: 1 (6ms lp) 6.12 address 13: burst repetition burst repetition (brep) is a feature that enables the qt2160 to make multiple measurements and take the average result; this improves the device?s ability to operate in noisy environments. the number of burst repetitions can be reduced in low noise environments for faster response time. the brep value can range between 1 and 63 repetitions. do not set to 0 as it is not valid. default value: 1 (one measurement burst) 6.13 address 15...16: ne g/pos drift compensation signals can drift because of changes in cx and cs over time and temperature. it is crucial that such drift be compensated, else false detections and sensitivity shifts can occur. drift compensation (see figure 6-1 ) is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect. the rate of adjustment must be performed slowly, otherwise legitimate detections could be ignored. the parameters can be configured in increments of 0.16s. table 6-12. burst repetition address b7 b6 b5 b4 b3 b2 b1 b0 13 0 0 brep table 6-13. neg/pos drift compensation address b7 b6 b5 b4 b3 b2 b1 b0 15 0 ndrift 16 0 pdrift
28 at42qt2160 [datasheet] 9502c?at42?09/2014 figure 6-1. thresholds and drift compensation the device drift compensates using a slew-rate limited ch ange to the reference level; the threshold and hysteresis values are slaved to this reference. when a finger is sensed, the signal falls since the human body acts to absorb charge from the cross-coupling between x and y lines. an isolated, untouched foreign object (a co in, or a water film) will cause the signal to rise very slightly due to an enhancement of coupling. this is contrary to the way most capacitive sensors operate. once a finger is sensed, the drift compensation mechanism ceases since the signal is legitimately detecting an object. drift compensation only works when the signal in question has not crossed the negative threshold level. the drift compensation mechanism can be asymmetric; the drift-compensation can be made to occur in one direction faster than it does in the other simply by changing the ndrift and pdrift setup pa rameters. this is a global configuration. specifically, drift compensation should be set to com pensate faster for increasing signals than for decreasing signals. decreasing signals should not be compensated qui ckly, since an approaching finger could be compensated for partially or entirely before even touching the touchpad (ndrift). however, an obstruction over the sense pad, for which the sensor has already made full allowance, could suddenly be removed leaving the sensor with an artificially suppre ssed reference level and thus become insensitive to touch. in this latter case, the sensor should compensate for the object's removal by raising the reference level relatively quickly (pdrift). drift compensation and the detection time-outs work together to provide for robust, adaptive sensing. the time-outs provide abrupt changes in reference calibration depending on the duration of the signal event. if pdrift or ndrift is set to 0 then the drift compensation in the respective direction is disabled. note: it is recommended that the drift compensation rate be mo re than four times the lp mode period. this is to prevent undersampling, which decreases the algorithm's efficiency. default ndrift: 20 (3.2 s/reference level) default pdrift: 5 (0.8 s/reference level) 6.14 address 17: de tect integrator ndil is used to provide signal filtering. threshold signal hysteresis reference output table 6-14. detect integrator address b7 b6 b5 b4 b3 b2 b1 b0 17 0 0 0 ndil
29 at42qt2160 [datasheet] 9502c?at42?09/2014 to suppress false detections caused by spurious events li ke electrical noise, the device incorporates a 'detection integrator' or di counter mechanism. a per-key counter is incremented each time the key has exceeded its threshold and stayed there for a number of acquisitions in succession, without going below the threshold level. when this counter reaches a preset limit the key is finally declared to be touched. if on any acquisition the signal is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. the qt2160 has a built in minimum of 1 di counts in addition to the ndil value. therefore, if setting a ndil value of 3, the actual number of consecutive acquisitions is 4. available ndil values are from 1 to 31. default: 3 (4 di value) 6.15 address 18: ne gative recal delay if an object unintentionally contacts a key resulting in a detection for a prolonged interval it is usually desirable to recalibrate the key in order to restore its function, perhaps after a time delay of some seconds. the negative recal delay timer monitors such detections; if a detection event exceeds the timer's setting, the key will be automatically recalibrated. after a recalibration has taken place, the affected key will once again function normally even if it is still being contacted by the foreign object. this feature is set globally. nrd can be disabled by setting it to zero (infinite timeout) in which case the key will never auto-recalibrate during a continuous detection (but the host could still command it). nrd is set globally, which can range in value from 1 to 255. nrd above 0 is expressed in 0.16 s increments. default: 255 (40.8 s) 6.16 address 19: drift hold time/awake timeout the dht/awake value is used for drift ho ld time and awake timeout parameters. drift hold time (dht) this is used to restrict drift on all keys while one or more keys are activated. dht defines the length of time the drift is halted after a key detection. this feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore creat e a sensitivity shift, and ultimately inhibit any touch detection. table 6-15. negative recal delay address b7 b6 b5 b4 b3 b2 b1 b0 18 nrd table 6-16. drift hold time/awake timeout address b7 b6 b5 b4 b3 b2 b1 b0 19 dht/awake
30 at42qt2160 [datasheet] 9502c?at42?09/2014 awake timeout (awake) after each matrix scan, the part will automatically go to sleep whenever possible to conserve power, unless there has been a key state change. the awake timeout feature determines how long the device will remain in the minimum lp mode from the last key state change. subsequent key state changes reinitialize the awake interval. once the part has been awakened by a change, the key response time will be fast for as lo ng as the keyboard remains in use. once key activity lapses for a period longer than the awake timeout, the part will return to the assigned lp mode. dht/awake can be configured to a value of between 0.32s and 40.8s, in increments of 0.16s. values of 0 and 1 are invalid and should not be used. note: it is recommended having a dht/awake of at least two seconds to prevent unintended key sensitivity drifts and the slider being unresponsive in longer lp modes. dht/awake default: 25 (4 s) 6.17 address 20: slider control hsyt: set the hysteresis value for the slider?s reported posit ion. hysteresis is the number of positions the user has to move back, before the new touch position is reported when the direction of scrolling is changed and during first scroll after touch down. at lower resolutions, where skipping of reported positions will be noticed, hysteresis can be set to 0 (1 position). at higher resolutions (6 ? 8 bits), it would be recommended to have a hysteresis of at least 2 positions or more. hyst can range from 0 (1 position) to 15 (16 positions). th e hysteresis is carried out at 8 bits resolution internally and scaled to the desired resolution; therefore at resolutions lower than 8 bits, there might be a difference of 1 reported position from the hyst setting, depending on where the touch down is. note: it is not valid to have a hysteresis value more than the available positions in a resolution. for example, do not have a hyst of 5 positions with a resolution of 2 bits (4 positions). num_keys: set the number of keys to be used in the slider. for proper slider operation, valid values are between 2 and 8. setting a value of 0, will disable the slider. hyst default: 0 (1 position), num_keys default: 5 (5 keys) table 6-17. slider control address b7 b6 b5 b4 b3 b2 b1 b0 20 hyst num_keys
31 at42qt2160 [datasheet] 9502c?at42?09/2014 6.18 address 21: slider options resolution: resolution of reported position of touch on the slider. valid values are between 0 (8 bits) to 6 (2 bits). the keys used for the slider starts at x0 and is on the y0 line. note: for better stability of the reported position at higher re solutions, increase the number of keys used to construct the slider, reduce the front panel thickness, reduce the loading on the slider keys or increase the burst length to gain more signal. default: 4 (4 bits) 6.19 address 22 ? 37: key control aks group: these bits configure which aks group a key is within (0 - aks disabled, 1, 2 or 3). keys in the same group cannot both be in detect at the same time, unless they both form part of the slider (see section 3.9.2 on page 14 ). default: 0 (aks disabled) table 6-18. slider options address b7 b6 b5 b4 b3 b2 b1 b0 21 0 0 0 0 0 resolution table 6-19. resolution value resolution value resolution 0 8 bits (0-255) 4 4 bits (0 ? 15) 1 7 bits (0-127) 5 3 bits (0 ? 7) 2 6 bits (0-63) 6 2 bits (0 ? 3) 3 5 bits (0-31) table 6-20. key control address b7 b6 b5 b4 b3 b2 b1 b0 22 ? 37 0 0 0 0 0 0 aks group
32 at42qt2160 [datasheet] 9502c?at42?09/2014 6.20 address 38 ? 53: negative threshold the negative threshold value is established relative to a key signal reference value. the threshold is used to determine key touch when crossed by a negative-going si gnal swing after having been filtered by the detection integrator. larger absolute values of threshold desensitize ke ys since the signal must travel farther in order to cross the threshold level. conversely, lower thresholds make keys more sensitive. as cx and cs drift, the reference point drift-compensates for these changes at a user-settable rate; the threshold level is recomputed whenever the reference point moves, and thus it also is drift compensated. the amount of nthr required depends on the amount of signal swing that occurs when a key is touched. thicker panels or smaller key geometries reduce key gain , that is, signal swing from touc h, thus requiring smaller nthr values to detect touch. negative hysteresis: this is fixed at two less than the negative threshold value and cannot be altered. it is implemented to stop keys from dithering in and out of detect. nthr typical values : 7 to 12 nthr default value: 10 (10 counts of threshold) 6.21 address 54 ? 69: burst length the qt2160 uses a fixed number of pulses which are executed in burst mode. this number is set in groups of four. therefore, the value send to the qt2160 is multiplied by four to get the actual number of burst pulses. the burst length is the number of times the charge-transfe r (qt) process is performed on a given key. each qt process is simply the pulsing of an x line once, with a corresponding y line enabled to capture the resulting charge passed through the key capacitance cx. increasing burst length directly affects key sensitivity. this occurs because the accumulation of charge in the charge integrator is directly linked to the burst length. the burst length of each key can be set individually, allowing for direct digital control over the signal gains of each key individually. apparent touch sensitivity is also controlled by t he negative threshold level (nthr). burst length and nthr interact; normally burst lengths should be kept as short as possible to reduce scan time and limit rf emissions, but nthr should be kept above 6 to reduce false detections due to external noise. the detection integrator mechanism also helps to prevent false detections. note: setting a burst length of zero for a specific key, disables that key. typical values : 8 ? 32 (32 ? 128 burst pulses) default: 4 (16 burst pulses) table 6-21. negative threshold address b7 b6 b5 b4 b3 b2 b1 b0 38?53 threshold table 6-22. burst length address b7 b6 b5 b4 b3 b2 b1 b0 54?69 burst length
33 at42qt2160 [datasheet] 9502c?at42?09/2014 6.22 address 70 ? 71: gpio/gpo drive if the gpios are set to outputs, the drive for the individual gpio is set according to the corresponding bit in gpio drive bytes. setting the bit to 1 will drive the corresponding gpio pin to vdd, while setting it to 0, will drive the corresponding gpio pin to ground. enabling pwm on a gpio pin will override the drive on the pin. shared x line gpos will be only driven when not doing an y measurements. during measurements, burst pulses will be driven from the x lines, make sure that the driven device will not be affected. default: 0 (all driven low) 6.23 address 73: gpio direction sets the direction of the gpios: 1 = driven outputs, 0 = floating inputs. if set as inputs, the gpio will only be read every 16ms (fixed cycle time). shared x line gpos are always outputs. by default, the dedicated gpios are set as inputs. make sure to drive (set to outputs) these gpios if not used, as floating pins may consume unnecessary current. default: 0 (all inputs) 6.24 address 74 ? 75: gpio/gpo pwm setting the corresponding gpio pwm bit to 1 will enable pw m on the respective pin. the pin will be driven according to the duty cycle specified in pwm level (address 76). pwm will only be enabled on gpios that have their gpio direction set to 1 (output). shared x line gpos will only be driven when not doing an y measurements. during measurements, burst pulses will be driven from the x lines, making sure that the driven device will not be affected. table 6-23. gpio/gpo drive address b7 b6 b5 b4 b3 b2 b1 b0 70 x7 x6 x5 x4 x3 x2 x1 x0 71 0 0 0 gpio3 gpio2 gpio1 0 0 table 6-24. gpio direction address b7 b6 b5 b4 b3 b2 b1 b0 73 0 0 0 gpio3 gpio2 gpio1 0 0 table 6-25. gpio/gpo pwm address b7 b6 b5 b4 b3 b2 b1 b0 74 x7 x6 x5 x4 x3 x2 x1 x0 75 0 0 0 gpio3 gpio2 gpio1 0 0
34 at42qt2160 [datasheet] 9502c?at42?09/2014 all pwm enabled gpios/gpos will only be switched when not doing any measurements. therefore, the pwm duty cycle?s accuracy will depend on the burst lengths of keys, as the longer the burst length, the longer the periods of no pwm switching. default: 0 (pwm disabled) 6.25 address 76: pwm level this sets the duty cycle of the pwm enabled pins. valid values are between 0 to 255. a value of 0 ? 10 will be 100% duty cycle (always on), and a value of 250 ? 255 will be 0 percent duty cycle (always off). default: 0 (100% duty cycle) 6.26 address 77 : gpio wake if the corresponding bit is set to 1, dedicated gp io pins set to input s will still be read during sleep mode (no capacitive sensing carried out). when a change in the state of the inputs is detected, the change line will be triggered and the qt2160 will go back to sleep. default: 0 (wake disabled) 6.27 address 78 ? 79: common change keys k0?k15: represents the respective keys. if set to 1, the respective key is included in the common change comparisons. note: if no keys are included in the common change group, the cc bit is set to 1. default: 0 (not included) table 6-26. pwm level address b7 b6 b5 b4 b3 b2 b1 b0 76 duty_cyc table 6-27. gpio wake address b7 b6 b5 b4 b3 b2 b1 b0 77 0 0 0 gpio3 gpio2 gpio1 0 0 table 6-28. common change keys address b7 b6 b5 b4 b3 b2 b1 b0 78 k7 k6 k5 k4 k3 k2 k1 k0 79 k15 k14 k13 k12 k11 k10 k9 k8
35 at42qt2160 [datasheet] 9502c?at42?09/2014 6.28 address 100 ? 163: si gnals and references addresses 100 ? 131 allow signal data to be read for each key. there are two bytes of data for each key. these are the key 16-bit signal which is accessed as two 8-bit bytes, stored lsb first. addresses 132 ? 163 allow reference data to be read for each key. there are two bytes of data for each key. these are the key 16-bit reference which is accessed as two 8-bit bytes, stored lsb first. there are a total of 16 keys and 4 bytes of data per key, yielding a total of 64 addresses. these addresses are read- only. table 6-29. signal and references address b7 b6 b5 b4 b3 100 0 signal lsb 132 0 reference lsb 101 0 signal msb 133 0 reference msb 102 1 signal lsb 134 1 reference lsb 103 1 signal msb 135 1 reference msb 104?131 2...15 136 ? 163 2?15
36 at42qt2160 [datasheet] 9502c?at42?09/2014 7. setups block setups data is sent from the host to the q160 using the i 2 c interface. the setups block is memory mapped onto this interface. thus each setup can be accessed by reading/writing the appropriate address. setups can be accessed individually or as a block. table 7-1. setups table address bytes parameter symbol valid range bits key scope default value description page 12 1 lp mode lp_mode 0 ? 255 8 16 1 0: sleep mode (no capacitive sensing) 1 ? 255: low power mode, increments in steps of 16 ms 26 13 1 burst repetition brep 1?63 6 16 1 range is 1 ? 63 burst repetitions 27 15 1 neg drift comp ndrift 0 ? 127 7 16 20 range is in 0.16 s increments, 1 = 0.16 s/reference level 27 16 1 pos drift comp pdrift 0 ? 127 7 16 5 range is in 0.16 s increments, 1 = 0.16 s/reference level 27 17 1 normal di limit ndil 1?31 5 16 3 normal di limit: take the operand and add 2 to get the value 28 18 1 neg recal delay nrd 0 ? 255 8 16 255 (40.8 s) range is in 0.16 s increments; 0 = infinite; default = 40.8 s range is {infinite, 0.16 ? 40.8 s} 29 19 1 drift hold time/awake timeout dht/awake 2 ? 255 8 16 25 (4s) range in 0.2 s increments; default = 4 s 29 20 1 slider control hyst 0?15 4 slider 0 (1 position) 0 ? 8: hysteresis for slider reported position 30 num_keys 0, 2?8 4 slider 5 (5 keys) 0: disables slider mode 2 ? 8: number of keys in slider slider keys start at x0 and are on y0 21 1 slider options resolution 0?6 3 slider 25 (4 s) resolution of reported slider touch position 8 bits (0) to 2 bits (6) 31 22?37 16 key control key_cont 0?3 3 1 0 (aks off) 0: aks disabled 1 ? 3: aks groups 31 38?53 16 neg threshold nthr 1 ? 255 8 1 10 32 54?69 16 burst length bl 0 ? 255 8 1 4 (16 pulses) 0: key disabled 1 ? 255: burst length = bl 4 32
37 at42qt2160 [datasheet] 9502c?at42?09/2014 70 1 gpo drive 1 x7 0?1 1 0 0: gpo driven low 1: gpo driven high 33 x6 0?1 1 ? 0 x5 0?1 1 ? 0 x4 0?1 1 ? 0 x3 0?1 1 ? 0 x2 0?1 1 ? 0 x1 0?1 1 ? 0 x0 0?1 1 ? 0 71 1 gpio drive 2 ? ? 1 ? 0 if gpio set to output, 0: gpio driven low 1: gpio driven high 33 ? ? 1 ? 0 ? ? 1 ? 0 gpio3 0?1 1 ? 0 gpio2 0?1 1 ? 0 gpio1 0?1 1 ? 0 ? ? 1 ? 0 ? ? 1 ? 0 73 1 gpio direction ? ? 1 ? 0 0: gpio is floating input 1: gpio is push-pull output 33 ? ? 1 ? 0 ? ? 1 ? 0 gpio3 0?1 1 ? 0 gpio2 0?1 1 ? 0 gpio1 0?1 1 ? 0 ? ? 1 ? 0 ? ? 1 ? 0 74 1 gpo pwm 1 x7 0?1 1 ? 0 0: pwm disabled 1: pwm enabled 33 x6 0?1 1 ? 0 x5 0?1 1 ? 0 x4 0?1 1 ? 0 x3 0?1 1 ? 0 x2 0?1 1 ? 0 x1 0?1 1 ? 0 x0 0?1 1 ? 0 table 7-1. setups table (continued) address bytes parameter symbol valid range bits key scope default value description page
38 at42qt2160 [datasheet] 9502c?at42?09/2014 75 1 gpio pwm 2 ? ? 1 ? 0 if gpio set to output, 0: pwm disabled 1: pwm enabled 33 ? ? 1 ? 0 ? ? 1 ? 0 gpio3 0?1 1 ? 0 gpio2 0?1 1 ? 0 gpio1 0?1 1 ? 0 ? ? 1 ? 0 ? ? 1 ? 0 76 1 pwm level duty_cyc 0 ? 255 8 gpios 0 if pwm enabled, 0 ? 10: 100% duty cycle (always on) 11 ? 249: varying duty cycles 250 ? 255: 0% duty cycle (always off) 34 77 1 gpio wake ? ? 1 ? 0 if gpio set to output, 0: gpio not read in sleep 1: gpio read in sleep 34 ? ? 1 ? 0 ? ? 1 ? 0 gpio3 0?1 1 ? 0 gpio2 0?1 1 ? 0 gpio1 0?1 1 ? 0 ? ? 1 ? 0 ? ? 1 ? 0 78?79 2 common change keys k0?k15 0?1 16 16 0 34 table 7-1. setups table (continued) address bytes parameter symbol valid range bits key scope default value description page
39 at42qt2160 [datasheet] 9502c?at42?09/2014 8. getting started with the qt2160 8.1 using the i 2 c bus the qt2160 is an address-mapped part. all commands an d data transfers consist of reads from, and writes to, memory locations. 8.2 establishing contact to establish that the device is present and running, write a zero to it (see section 8.3 ). now read a single byte (see section 8.4 ). this byte should be the id of the device (0x11). if this is the case the device is present and running. 8.3 writing to the device a write cycle to the device consists of a start condition followed by the i 2 c address of the device (see section 5.1 ). the next byte is the address of the location into which the writing will start. this address is then stored as the address pointer. subsequent bytes in a multi-byte transfer will be written to the location of the address pointer, location of the address pointer + 1, location of the address pointer + 2, and so on. this ends with the stop condition on the i 2 c bus. a new write cycle will involve sending another address pointer. it is possible to stop the write after the address pointer is sent if no data is required to be written to the device. this is done when setting the address pointer for reading data. 8.4 reading from the device a read cycle consists of a start condition followed by the i 2 c address of the device (see section 5.1 ). bytes can then be read starting at the location pointed to by the address pointer set by the last write operation. the address is internally incremented for each byte read during a multi-byte read. the stop condition at the end of the transfer causes the internal address pointer to revert to the value written during the last write operation. this means that if a set of data bytes needs to be read many times (such as the status bytes) then it is not necessary to keep sending an address pointer. it can be set to the first location and multi-byte reads will always then start there. 8.5 keys the default setting of the qt2160 is for 16 keys with aks disabled. this will be the default setting when the device first powers up. a coin placed over any key can be used to pick up the burst signal to see the activity on the keys as explained in section 3 of the application note secrets of a successful touch sensor design which can be downloaded from the atmel website. the change line will go low indicating there is new data to be read. reading the status bytes (address 2 ? 6) will cause the change line to go inactive, as the data has been read. if a key is now touched, the change line will go active again, indicating that there is new data again. the change line will remain active until the status location containing the status for that key is read. if the change line does not go low then it is likely the sensitivity of the key is not high enough. the burst length should be increased to increase the sensitivity. a change in burst length should be followed by a calibration command (set the calibration byte to a non-zero value) to ensure reliable operation. it is also possible to adjust the sensitivity using the negative threshold for that key. note that thresholds below 6 counts may cause sensitivity to noise and thresholds above 12 counts will require longer burst lengths than strictly necessary. all unused keys should be switched off by setting their burst lengths to zero. this will reduce the power requirements of the device.
40 at42qt2160 [datasheet] 9502c?at42?09/2014 8.6 slider a group of keys on the y0 line can be configured as a slider . these have to be placed in numerical order starting with x0 and with no missing keys in the sequence. the keys should be 5 ? 7 mm wide along the length of the slider for good linearity. the number of keys needed in a slider will simply be the number of the size required to form the desired slider length. the slider can now be enabled by setting the num_keys bits in slider control byte to the number of keys which are used in the slider. this can be from 2 to 8 keys. for exampl e, to enable a slider of five keys, set num_keys to five. note that the higher the resolution, the more keys will be required to get a stable response out of the slider. as a general rule, the number of keys must be at least the number of bits, for example, at least 4 keys for a 4 bit slider. now the slider is enabled, touching it will result in a slid er position being reported in the slider touch position byte. note that the keys forming the slider will still cause key detections and will still report their status in the key status registers. if the slider position is noisy, try reducing the panel thickness or increasing the sensitivities of the keys forming the slider, to get more signal for positional calculations. increasing the hysteresis ( section 3.2 on page 8 ) will also help. keys within the same slider are normally in the same aks group and have the same burst length and threshold. 8.7 adjacent key suppre ssion (aks) technology adjacent key suppression (aks) technology is a patented method to detect which key is pressed, when keys are located close together. a touch in a group of aks keys will only be indicated on the key with the largest signal. this is assumed to be the intended key. once a key in an aks group is in detec t, there can be no fu rther detections on keys in that group until the key is released. by default, the aks technique is disabled on all keys; therefore, the keys can detect, regardless of the state of any other keys. the aks technology works slightly differently when keys are in a slider which act like a single aks object. any number of keys can go into detect with a slider but if any keys within one of these objects are in detect then the aks technology will lock ou t anything else in the same aks group. similarl y, a key in the same aks group as the slider can lock out the slider as a whole object. note: for normal operation all keys in the slider should be placed in the same aks group.
41 at42qt2160 [datasheet] 9502c?at42?09/2014 8.8 gpios by default, the dedicated gpios (gpio1 ? gpio3) are set as inputs. make sure to drive (set to outputs) these gpios if not used, as floating pins may consume unnecessary current. by default, shared gpos are push-pull outputs driven low when not measuring. table 8-1 shows a summary of the gpio options, and the precedence of each setting. 8.9 typical initialization and usage figure 8-1 on page 42 shows a typical example of communicating with the qt2160. 1. after a reset/power-up, wait for change to go low, indicating the qt2160 has initialized and is ready to communicate. 2. send all the setup parameters that need to be changed from the startup default values. drive all unused gpios to outputs, to prevent unnecessary increase in current consumption. 3. after setting up the qt2160, send a calibrate command. 4. read all status bytes once (address 2 to 6), to return the change line to an inactive state. 5. if change line goes low, perform a read of the required status byte. all the status bytes that have changed need to be read, to ensure that the change line goes inactive again. 6. process the received byte accordingly. 7. check the reset bit in the general status byte (address 2). if it is a 1, go to step 2 to resend all the setup param- eters, as a reset has occurred. if it is a 0, proceed to the next step. 8. repeat steps 5, 6 and 7. steps 5 and 6 are the continuous normal operating loop sequence after initialization. table 8-1. gpio options gpio direction gpio pwm gpio drive wake dedicated gpio function shared gpo function 0 x x x input - read only in lp mode so change event possible only in lp mode always output 0 x x 1 input - read in lp and sleep modes so change event possible in both modes always output 1 0 0 x output - gnd output ? gnd 1 0 1 x output - vdd output ? vdd 1 1 x x output - pwm output - pwm
42 at42qt2160 [datasheet] 9502c?at42?09/2014 figure 8-1. typical initialization and usage send setup parameters to set up qt2160 reset/power up /change pin active (low)? send calibrate command read all status bytes (address 2...6) to restore /change pin to inactive (high) read required status bytes and other status bytes that changed, to restore /change pin to inactive (high). /change pin active (low)? host processes received status bytes no yes no yes reset occurred bit = 1? no yes
43 at42qt2160 [datasheet] 9502c?at42?09/2014 9. specifications 9.1 absolute maximu m specifications 9.2 recommended op erating conditions vdd ?0.5 to +6 v max continuous pin current, any control or drive pin 10 ma short circuit duration to ground, any pin infinite short circuit duration to vdd, any pin infinite voltage forced onto any pin ?0.6 v to (vdd + 0.6) v caution: stresses beyond those listed under ?absolute maximum specifications" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum specification conditions for extended periods may affect device reliability. operating temp ?40 o c to +85 o c storage temp ?55 o c to +125 o c vdd +1.8 v to 5.5 v supply ripple+noise (1) (<1mhz) 1. applicable to qt2160 on a typical setup, with burst repetition (brep) = 2. the effects of supply ripple and noise on performance is more prominent the nearer it is to the burst center frequency. 25 mv supply ripple+noise (1) (>1mhz) 50 mv cx transverse load capacitance per key 2 to 20 pf
44 at42qt2160 [datasheet] 9502c?at42?09/2014 9.3 dc specifications 9.4 timing specifications vdd = 5.0 v, cs = 4.7 nf, rs = 1 m ? , ta = recommended range, unless otherwise noted parameter description min typ max units notes iddr average supply current, running (lp16ms) ? 476 955 1127 ? a vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v idds average supply current, sleeping (sleep) ? <1.5 <2 <3 ? a vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v vil low input logic level ? ? 0.2 vdd v 1.8 v < vdd < 5 v vhl high input logic level 0.6 vdd ? ? v 1.8 v < vdd < 5 v vol low output voltage ? ? 0.2 v voh high output voltage 4.2 ? ? v iil input leakage current ? ? 1 a ar acquisition resolution ? 10 ? bits rrst internal rst pull-up resistor ? ? 60 k ? parameter description min typ max units notes t bs burst duration ? 40 80 120 160 ? s bl = 4 (4 4 = 16 actual pulses) bl = 8 (8 4 = 32 actual pulses) bl = 12 (12 4 = 48 actual pulses) bl = 16 (16 4 = 64 actual pulses) fc burst center frequency ? 400 ? khz fm burst modulation, percentage ? 8 ? % t dw dwell time 250 ? 500 ns t pw pulse width ? 1000 ? ns
45 at42qt2160 [datasheet] 9502c?at42?09/2014 9.5 i 2 c bus specifications 9.6 power consumption parameter unit address space 7-bit maximum bus speed (scl) 100 khz hold time start condition 4 s minimum setup time for stop condition 4 s minimum bus free time between a stop and start condition 4.7 s minimum rise times on sda and scl 1 s maximum table 9-1. average current consumption test condition: 16 keys enabled, bl = 16 (4 16 = 64 actual pulses), brep = 1 lp mode idd (a) at vdd = 1.8 v 3.3 v 5v sleep <1.5 <2 <3 lp 16 ms 476 955 1,127 lp 32 ms 311 609 770 lp 64 ms 229 436 592 lp 128 ms 188 350 502 lp 256 ms 167 306 458 lp 512 ms 157 285 435 lp 1024 ms 152 274 424
46 at42qt2160 [datasheet] 9502c?at42?09/2014 9.7 mechanical dimensions
47 at42qt2160 [datasheet] 9502c?at42?09/2014 9.8 marking either part marking can be supplied: 1 28 pin1id at42 -mmu ltcode qt2160 chip assembly lotcode (for traceability) part number; at42qt2160-mmu 1 28 pin 1 id ltcode chip assembly lotcode (for traceability) 2160 at program week code number 1-52 where: a = 1, b = 2...z = 26 then using the underscore a = 27...z = 52 abbreviation of part number; at42qt 2160
48 at42qt2160 [datasheet] 9502c?at42?09/2014 9.9 part numbers 9.10 moisture sensitivity level (msl) part number description at42qt2160-mmu 28-pin 4 x 4mm mlf rohs compliant ic msl rating peak body temperature specifications msl3 260 o c ipc/jedec j-std-020
49 at42qt2160 [datasheet] 9502c?at42?09/2014 10. known issues the following errata are applicable for qt2160: 1. i2c interface malfunct ion in multi-slave designs description: if the device wakes up from low power mode during an i2c transfer on the bus, the device may start to clock in data, depending on the level on sda and scl. if this state occurs while transferring the last byte in the data, the device detects the stop condition as illegal and triggers an interrupt with bus error. this may cause the sda line to be pulled low for a short duration. if the device wakes up during a byte transfer that is not the last, and the i2c address is clocked on the data line by accident, this triggers an interrupt with a legal value. the chip may start communicating and corrupts the ongoing communication. worst case, this may corrupt the setup parameters stored in at42qt2160. problem fix / workaround: use a dedicated i2c bus for each at42qt2160. do not share the bus with any other slave devices. 2. bus free time between a stop and start condition description : the bus free time between a stop and start condition is specified as 4.7 s as per i2c bus specification. this free time is insufficient for the at42qt2160 device and may cause random communication failure, especially during read operation. problem fix / workaround: provide a minimum 50 s bus free time between a stop and start condition to ensure reliable communication.
50 at42qt2160 [datasheet] 9502c?at42?09/2014 revision history revision no. history revision ax ? july 2008 ? initial release revision b ? march 2013 ? general updates ? applied new template revision c ? september 2014 ? added section ?known issues? on page 49
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